The present invention relates to a substrate of a semiconductor integrated circuit device (or semiconductor device) and a gate structure thereof, and a technique useful in application to Front End of Line (FEOL) process technology in a method for manufacturing a semiconductor integrated circuit device (or semiconductor device).
The Unexamined Japanese Patent Publication (JP-A) No. 2009-94369, hereinafter referred to as “Patent Document 1”, and the US Patent Publication No. 2009-96036 corresponding to it, hereinafter referred to as “Patent Document 2” disclose a technique for forming a bulk region in part of SOI (Silicon on Insulator) wafer.
The Japanese Translation of PCT International Application Publication (JP-T) No. 2008-523591 (Patent Document 3), and the U.S. Pat. No. 7,663,192 (Patent Document 4) corresponding to it disclose a single High-k/dual metal type gate-last process.
The JP-T-2009-545168 (Patent Document 5) and the International Publication WO 2008/14038 (Patent Document 6) corresponding to it disclose a so-called FUSI (Fully Silicided) gate technology.
The JP-A-2011-49282 (Patent Document 7) discloses a technique for providing, in a bulk substrate structure, both MISFET (Metal Insulator Semiconductor Field Effect Transistor) having a polycrystalline silicon gate electrode structure according to a gate-first method, and MISFET having a metal gate electrode structure according to a gate-last method.
A technique for controlling, by means of a back gate bias, the threshold voltage of a transistor, and other various properties thereof is disclosed by R. Tsuchiya and other eight in “Silicon on Thin BOX: A New Paradigm of The CMOSFET for Low-Power and High-Performance Application Featuring Wide-Range Back-Bias Control”, IEDM Tech. 2004, pp. 631-634 (Nonpatent Document 1).